1. Field of the Invention
The present invention relates to verification of electronic circuit designs and more particularly to accelerating verification of current circuit design by the acceleration of software simulators and emulation of electronic designs by means of reprogrammable devices such as a Field Programmable Gate Array (FPGA). More particularly the invention can relate to the accelerated verification by automatic retargeting of Application Specific Integrated Circuits (ASIC) designs and High Definition Logic (HDL) designs in general, into reprogrammable devices of the specified kind.
2. Background Information
Today's ASIC designs have tens of millions of gates. To verify these designs, software simulators such as the NC-Sim from Cadence Design, VCS Simulator from Synopsys and Riviera and an Active-HDL from Aldec, Inc. of Las Vegas, Nev. may be used. However, since the number of gates in ASIC designs is growing faster than the speed of computers, there is a need to accelerate the operation of design simulators to verify these designs.
One approach is to simulate at higher levels of abstraction such as the simulator by SystemC, Behavioral VHDL, or SystemVerilog. However, these simulators require sophistication and costly compilers that are still under development, and their performance gains are not sufficient for efficient verification of the newest and largest ASIC devices.
Another approach is to accelerate the existing software simulators or use emulation in place of simulation altogether. Such accelerators and emulators, based on reprogrammable devices, have been manufactured by Quickturn, Inc. and Ikos, Inc. Their major drawback is that in order to reproduce basic design behavior in reprogrammable devices, hundreds of engineering hours must be spent on manual conversion of ASIC clocking chains into clocking chains running in the FPGA devices.
The power dissipation has become such an enormous problem in the large ASIC design devices that they employ as many as 20 or 40 clocks instead of one system clock that synchronizes all data transfers between flip-flops and latches. Since gates and their interconnections in reprogrammable devices have different timings from gates and interconnection in the ASIC design, an enormous amount of mental effort and time is needed to assure reliable conversion of ASIC designs into reprogrammable devices so they can emulate ASIC design behavior. The purpose of the present invention is to insure automatic conversion of ASIC designs into reprogrammable devices.
It is therefore one object of the present invention to accelerate the verification of new, very large ASIC designs.
Yet another object of the present invention is to provide a system and apparatus for accelerating the verification of very large ASIC designs by accelerating the simulation of the designs.
It is one object of the present invention to provide automatic conversion of ASIC designs into reprogrammable devices for quick, functional verification of the designs. This is accomplished by automatic conversion of ASIC clocking chains into clocking chains in reprogrammable devices so that these devices will behave functionally the same as the ASIC device.
Furthermore, another object of the present invention is to handle clocking of various flip-flops and latches, so that a wide variety of ASIC designs can be handled effectively and effortlessly by hardware accelerators, emulators and various ASIC prototyping equipment.
Still another object of the present invention is to provide a system and apparatus for accelerating the verification of very large ASIC designs by finding synchronous primitives in a circuit design files that are receiving clock signals from a clock source and inserting edge detectors such as between the clock sources and the synchronous primitives.
Yet another object of the present invention is to provide a method and apparatus for accelerating the verification of ASIC designs by finding synchronous primitives that do not have a clock enable input and replacing them with a synchronous primitive having a clock enable input.
Still another object of the present invention is to provide a method and apparatus for verification of ASIC designs including design verification managing software that analyzes connection between inputs of synchronous primitives and outputs from asynchronous primitives and insertion of a data buffer between these inputs.
Still another object of the present invention is to provide a method and apparatus for verification of ASIC designs in which the verification manager software finds falling-edge clocked primitives and substitutes rising clock-edge primitives for the falling clock-edge primitives.
Yet another object of the present invention is to provide an apparatus and method for verification of very large ASIC designs in which design verification manager software includes memory for storing ASIC designed files, design verification. manager software for processing the design files and simulator software for simulating the design files or selected parts thereof.
Yet another object of the present invention is to provide a method and apparatus for accelerating the verification of ASIC designs having a computer for storing design files, design verification manager software, simulation software and test bench files for stimulating simulator operations and a hardware accelerator. The design verification manager software splits design files into selected simulation files and hardware execution files that are downloaded into selected simulation files in said simulator and into selected hardware execution files in said hardware accelerator.